Coverage Extensibility in SystemVerilog-2023
Quite a while back I wrote a series of posts about coverage extensibility in SystemVerilog. In the first post we looked at how to use policy classes to imple...
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Creating UVM Tests Dynamically
Everyone who uses UVM knows that using the library ofter requires large amounts of boilerplate code. Tests are no exception.
Goodbye Blogger, Hello Static Site
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A Comparison of Formal and Simulation for a Simple, Yet Non-Trivial Design - Part 1
I’ve talked a lot about constrained random verification on the blog, but now it’s time to branch out to formal verification. As a fun first post on the topic...
Favor Composition Over Inheritance - Even for Constraints
Simulation is currently the dominant functional verification technique, with constrained random verification the most widely used methodology. While producin...