Recent Posts

Packages, Class Names and UVM

Some time ago I wrote a post that challenged some of the established coding conventions of modern SystemVerilog. In particular, I expressed my displeasure wi...

Accessing Multiple Registers at Once

As I already mentioned, I gave a talk at DVCon Europe this year on how to implement burst accesses to memories modeled using UVM_REG. The motivation for that...

How Do I Transfer Thee? Let Me Count the Ways

I’ll be giving a talk this week at DVCon Europe about how to use the UVM REG classes to verify memory sub-systems. In particular, I’ll focus on how to transl...

Of Copies and Clones

Let’s take a walk down memory lane and remember the fun times we had in college. For a few weeks at the end of the semester, though, things had to get seriou...